MTR-3N33-G-R-0-N-S三个定时器都使用一个中断IRQ5。定时器中断状态寄存器用于确定哪些计时器启动了中断。中断状态寄存器是一个通用输入寄存器，位于82C54外部，位于从电源管理基输入/输出地址偏移31h。中断状态寄存器地址可以通过首先确定PCI配置基址来找到对于设备ID 7113h和供应商ID 8086h。电源管理基本输入/输出地址可以通过从此PCI配置地址读取偏移量40h来找到。计时器中断状态寄存器位位于电源管理的偏移量31h处基址输入/输出地址，位5、6和7（参见图4-2）。从电源管理基本输入/输出地址读取偏移量31h的字节用于获取这些位。位5、6和7分别对应于计时器2、1和0，为了计时器中断状态寄存器

首先将零（0）写入通用输出寄存器，位于电源管理基座的偏移37h输入/输出地址位3、4和6（不是位3、4和5）。然后将1写在相同的重新启用定时器中断状态寄存器的位。位3、4和6对应于定时器2、1和0分别使用PC/AT的标准程序定时器中断IRQ5。有关使用82C54定时器的示例，请参阅附录D。VMIVME-7698计时器从500美元开始映射到输入/输出地址空间。请参阅表4-1计时器，由三个16位计时器和一个控制字寄存器组成（见图4-4）通过8位KJ1501X1-BB1数据总线读取/写入。定时器0、1和2这三个定时器在功能上是等效的。因此，只有
将描述单个计时器。图4-5是计时器的框图。每个计时器功能独立。尽管控制字显示在计时器块中它不是计时器的一部分，但其内容直接影响计时器的工作方式功能。如图4-5所示，当锁存时，状态寄存器包含当前控制字寄存器的内容以及输出和负载的当前状态计数标志（状态字可通过Read Back命令获得，请参阅第59页的“阅读”部分）。计时器标记为TE（计时器元素）。它是一个16位同步可预设向下柜台标记为OLM和OLL的块是8位输出锁存器（OL）。下标M和L代表0高有效字节和0低有效字节。这些插销通常跟踪TE，但在收到命令时，将锁定并保持当前计数，直到CPU读取计数。读取锁存计数时，OL寄存器将继续跟踪TE。读取OL寄存器时，必须执行两次8位访问以检索计时器的完整16位值，因为一次只启用一个锁存器。TE无法读取；从OL寄存器读取计数。A single interrupt, IRQ5, is used by all three Timers. A Timer Interrupt Status register
is provided in order to determine which Timer(s) initiated an interrupt. The interrupt
status register is a general-purpose input register located, external to the 82C54, at
offset 31h from the Power Management base I/O address. The interrupt status
register address can be found by first determining the PCI Configuration base address
for Device ID 7113h and Vendor ID 8086h. The Power Management base I/O address
can be found by reading offset 40h from this PCI Configuration address. The Timer
Interrupt Status register bits are located at offset 31h from the Power Management
base I/O address, bits 5, 6, and 7 (refer to Figure 4-2).A byte read of Offset 31h from the Power Management base I/O address is used to
obtain these bits. Bits 5, 6, and 7 correspond to Timers 2, 1, and 0, respectivelyIn order to clear the Timer Interrupt Status register, first write zeros (0’s) to the
general-purpose output register located at offset 37h of the Power Management base
I/O address bits 3, 4, and 6 (Not bits 3, 4 and 5). Then write ones (1’s) to these same
bits to re-enable the Timer Interrupt Status register. Bits 3, 4, and 6 correspond to
Timers 2, 1, and 0, respectivelyThe Timer Interrupts are cleared using the standard procedure for clearing PC/AT
IRQ5. Refer to Appendix D for an example of using the 82C54 timers.The VMIVME-7698 Timers are mapped in I/O address space starting at $500. See
Table 4-1. The Timers, consisting of three 16-bit timers and a Control Word Register
(see Figure 4-4) are read from/written to via an 8-bit data bus.The three Timers, Timer 0, 1, and 2, are functionally equivalent. Therefore only a
single Timer will be described. Figure 4-5 is a block diagram of a Timer. Each Timer is
functionally independent. Although the Control word is shown in the Timer block
diagram, it is not a part of the Timer, but its contents directly affect how the Timer现场运维工单派遣频繁，24小时ON CALL没商量？ABB助力运维法方式升级，从周期性运维到状态运维和预测性运维，预判你的预判，助你成为运筹帷幄的“全知全能”。